Gate driving apparatus

ABSTRACT

A gate driving apparatus is disclosed. The gate driving apparatus includes a first gate driving chip and N second gate driving chips, wherein N is positive integer. The first gate driving chip has a first input pin and a first current output pin. The first gate driving chip receives a reference electrical signal by the first input pin, and generates a reference current according to the reference electrical signal. The first current output pin is used for outputting the reference current. Each of the second gate driving chips has a current input pin for receiving the reference current and a second current output pin for outputting the reference current. The first gate driving chip and the second gate driving chips generate at least a first output signal and at least N second output signals according to the reference current.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan applicationserial no. 101119368, filed on May 30, 2012. The entirety of theabove-mentioned patent application is hereby incorporated by referenceherein and made a part of this specification.

BACKGROUND

1. Technical Field

The present invention is related to a gate driving apparatus.

2. Description of Related Art

Referring to FIG. 1, FIG. 1 is a block diagram illustrating aconventional gate driving apparatus 100. The conventional gate drivingapparatus 100 includes two gate driving chips 110 and 120 which areconnected in series with each other. The gate driving chip 110 has aninput pin INPAD1 and an output pin OUPAD1, the gate driving chip 120 hasan input pin INPAD2 and an output pin OUPAD2. Wherein, the output pinOUPAD1 of the gate driving chip 110 is coupled to the output pin INPAD2of the gate driving chip 120, and the input pin INPAD1 of the gatedriving chip 110 receives a voltage VB. A bias voltage circuit 112 ofthe gate driving chip 110 receives the voltage VB through the input pinINPAD1, and a functional block circuit 111 of the gate driving chip 110generates an output signal (a gate driving signal) GD1 according to thevoltage VB. Furthermore, in the gate driving chip 110, the input pinINPAD1 and the output pin OUPAD1 interconnects, and the voltage VB istransmitted to the bias voltage circuit 122 of the gate driving chip 120from the input pin INPAD1 through the output pin OUPAD1.

Two functional block circuits 111 and 121 respectively generate twooutput signals GD1 and GD2 according two currents I1 and I2, wherein thecurrents I1 and I2 are respectively generated by two bias voltagecircuits 112 and 122 according to the voltage VB. However, due to thevariation of the process parameters between the gate driving chips 110and 120, the currents I1 and I2 generated by the bias voltage circuits112 and 122 according to the voltage VB may not be uniform. Therefore,the output signals GD1 and GD2 generated respectively by the functionalblock circuits 111 and 121 are not uniform.

SUMMARY

The embodiment of the present invention provides a plurality of gatedriving apparatus to enable a plurality of gate driving chips within thegate driving apparatus not to generate the output signals with differentcharacteristics due of the fabrication variations.

The embodiment of the present invention provides a gate drivingapparatus, including a first gate driving chip and N second gate drivingchips, wherein N is a positive integer. The first gate driving chip hasan input pin and a first current output pin. The first gate driving chipreceives a reference electrical signal by the input pin, and generates areference current according to the reference electrical signal. Thefirst current output pin outputs the reference current. Wherein, thefirst gate driving chip and the second gate driving chips furthergenerate at least a first output signal and at least N output signalrespectively according to the reference current.

The embodiment of the present invention provides a gate drivingapparatus, including a plurality of gate driving chips and a currentgenerator. Each of the gate driving chips has a common pin, and thecommon pins of the gate driving chip are coupled to each other. One endof the current generator is coupled to the common pin of each gatedriving chip, and another end of the current generator is coupled to areference ground voltage. Wherein, each gate driving chip generates atleast an output signal, moreover, each gate driving chip enables theoutput signal to be pulled-up to a driving voltage or enables thecurrent generator to pull-down the output signal to a reference signalaccording to a control signal.

Base on the above, the embodiment of the present invention enables eachgate driving apparatus to generate an output signal according to theidentical reference currents received, wherein the identical referencecurrent is provided by the gate driving chips of the gate drivingapparatus. That is, variations in process parameters between each of thegate driving chips is not affect the characteristic of the outputsignals, hence, the uniformity of the output signals generated by thegate driving apparatus is enhanced effectively.

Several exemplary embodiments accompanied with figures are described indetail below to further describe the disclosure in details.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide further understanding,and are incorporated in and constitute a part of this specification. Thedrawings illustrate exemplary embodiments and, together with thedescription, serve to explain the principles of the disclosure.

FIG. 1 is a block diagram illustrating a conventional gate drivingapparatus 100.

FIG. 2 is a diagram illustrating a gate driving apparatus 200 accordingto an embodiment of the present invention.

FIG. 3A is a diagram illustrating a gate driving apparatus 300 accordingto another embodiment of the present invention.

FIGS. 3B-3C respectively illustrate different implementations of thegate driving apparatus 300 according to the embodiment of the presentinvention.

FIG. 4A is a diagram illustrating a gate driving apparatus 400 accordingto another embodiment of the present invention.

FIGS. 4B-4C respectively illustrate different implementations of thegate driving apparatus 400 according to the embodiment of the presentinvention.

FIG. 5A illustrates an implementation of a first gate driving chip ofthe gate driving apparatus according to the embodiment of the invention.

FIG. 5B illustrates an implementation of a selector 512 according to theembodiment of the present invention.

FIG. 6 is a diagram illustrating a gate driving apparatus 600 accordingto other one embodiment of the present invention.

FIG. 7A is a diagram illustrating a gate driving apparatus 700 accordingto other one embodiment of the present invention.

FIG. 7B illustrates an implementation of a programmable referenceelectrical signal generator 701 according to the embodiment of thepresent invention.

FIG. 8A is a diagram illustrating a gate driving apparatus 800 accordingto the embodiment of the present invention.

FIGS. 8B-8E respectively illustrate different implementations of thegate driving apparatus 800 according to the embodiment of the presentinvention.

FIGS. 9A-9C respectively illustrate different implementations of a gatedriving apparatus 900 according to the embodiment of the presentinvention.

DETAILED DESCRIPTION OF DISCLOSED EMBODIMENTS

Reference will now be made in detail to exemplary embodiments, examplesof which are illustrated in the accompanying drawings. The followingdescription refers to the accompanying drawings in which the samenumbers in different drawings represent the same or similar elementsunless otherwise represented. The implementations set forth in thefollowing description of exemplary embodiments consistent with thepresent invention do not represent all implementations consistent withthe invention. Instead, they are merely examples of systems and methodsconsistent with aspects related to the invention as recited in theappended claims.

Referring to FIG. 2, FIG. 2 is a diagram illustrating a gate drivingapparatus 200 according to an embodiment of the present invention. Thegate driving apparatus 200 includes a first gate driving chip 210 and aplurality of second gate driving chips 211-22N. The first gate drivingchip 210 has an input pin INPAD1 and a current output pin OUPAD1. Thesecond gate driving chips 221-22N have a plurality of current input pinsINPAD2-INPADN and a plurality of current output pins OUPAD2-OUPADNrespectively. In the present embodiment, the first gate driving chip 210receives a reference electrical signal ES1 through the input pin INPAD1.The first gate driving chip 210 generates a reference current IRaccording to the reference electrical signal ES1. Wherein, the referencecurrent IR is transmitted to the current output pin OUPAD1 of the firstgate driving chip 210, the reference current IR is then transmitted tothe second gate driving chips 221 of first level through the currentoutput pin OUPAD1.

The first gate driving chip 210 further includes a functional blockcircuit 221. In addition to the current output pin OUPAD1, the referencecurrent IR is also transmitted to the functional block circuit 211. Thefunctional block circuit 211 generates an output signal GD1 according tothe reference current IR received. In detail, the output signal GD1generated by the first gate driving chip 210 may be used as a gatedriving signal of a display panel. In other words, the output signal GD1is a signal used to drive the transition between high gate drivingvoltage level and low gate driving voltage level for a thin filmtransistor in a display panel. When the output signal GD1 istransitioned to a low gate driving voltage level from a high gatedriving voltage level, the functional block circuit 211 may pull-downthe voltage level of the output signal GD1 according to the referencecurrent IR.

In addition, the functional block circuit 211 may generate one or moreoutput signals GD1.

The current input pin INPAD2 of the second gate driving chips 221 andthe current output pin OUPAD1 of the first gate driving chip 210 arecoupled together. Moreover, the second gate driving chips 221 receivesthe reference current IR through the current input pin INPAD2, and thereference current IR is transmitted to the current output pin OUPAD2.Furthermore, the reference current IR is transmitted to the second gatedriving chips 221-22N through the coupling relationship between eachlevel of the second gate driving chips 221-22N.

The second gate driving chips 221-22N include a plurality of functionalblock circuits 2211-22N1 respectively. A plurality of output signalsGD2-GDN are respectively generated based on the reference current IRreceived by the functional block circuits 2211-22N1. It should be notedthat the reference currents IR received by the functional block circuits2211-22N1 of the second gate driving chips 221-22N and then used to pulldown the output signals GD2-GDN are the same reference currents IR.Moreover, the functional block circuit 211 of the first gate drivingchip 210 also pulls down the output signal GD1 generated by thefunctional block circuit 211 according to the reference current IR.Therefore, when the output signals GD1-GDN generated by the gate drivingapparatus 200 are pulled down to the low gate voltage level, thedropping rate of the output signals GD1-GDN do not vary with thevariation of the fabrication parameter between the first gate drivingchip 210 and the second gate driving chips 221-22N. In other words, theuniformity of the output signals GD1-GDN of the gate driving apparatus200 may be enhanced effectively.

In addition, the functional block circuits 2211-22N1 may generate one ormore output signals GD2-GDN.

Referring to FIG. 3A, FIG. 3A is a diagram illustrating a gate drivingapparatus 300 according to another embodiment of the present invention.The gate driving apparatus 300 includes a reference electrical signalgenerator IS1, a first gate driving chip 310, and a second gate drivingchip 321. In the present embodiment, the reference electrical signalgenerator IS1 is a current source, and coupled between an input pinINPAD1 of the first gate driving chip 310 and an operating voltage VCC.The reference electrical signal generator IS1 generates a referencesignal ES1 as a reference current IR. The reference current IR istransmitted to a functional block circuit 311 in the first gate drivingchip 310 and a current output pin OUPAD1 of the first gate driving chip310 through the input pin INPAD1.

A current input pin INPAD2 of the second gate driving chip 321 iscoupled to the current output pin OUPAD1 of the first gate driving chip310, and receives the reference current IR. The reference current IR isthen transmitted to the functional block circuit 3211 in the second gatedriving chip 321 and a current output pin OUPAD2 of the second drivingchip 321 through the current input pin INPAD2.

From the description above, the functional block circuit 311 in thefirst gate driving chip 310 and the functional block circuit 3211 in thesecond gate driving chip 321 receive identical reference current IR.Therefore, no variation is generated between the output signals GD1 andGD2 by the affect of the fabrication parameters between the first gatedriving chip 310 and the second gate driving chip 321, wherein theoutput signals GD1 and GD2 are respectively generated by the functionalblock circuit 311 and the functional block circuit 3211. In other words,the voltage uniformity of the output signals GD1 and GD2 generated bythe gate driving apparatus may be enhanced.

Referring to FIGS. 3B-3C, FIGS. 3B-3C respectively illustrate differentimplementations of the gate driving apparatus 300 according to theembodiment of the present invention. In FIG. 3B, the first gate drivingchip 300 further includes a current mirror MR11 and a current mirrorMR12. Wherein, the current mirror MR11 receives the reference electricalsignal ES1 provided by the electrical signal generator IS1, andgenerates the reference current IR by mirroring the reference electricalsignal ES1, wherein the reference electrical signal ES1 is a currentsignal. The current mirror MR12 receives and mirrors the referencecurrent IR generated by the current mirror MR11 in order to output thereference current IR at the current output pin OUPAD1 which the currentmirror MR12 is coupled to.

In addition, the current mirror MR12 further includes a transistor T1,and the reference current IR is transmitted to the functional blockcircuit 311 through a drain of the transistor T1. Wherein the transistorT1 transmits the reference current IR to the functional block circuit311 by a mirroring method with a ratio of 1:1.

The second gate driving chip 321 further includes a current mirror MR21and a current mirror MR22. The current mirror MR21 is coupled to thecurrent input pin INPAD2 of the second gate driving chip 321 to receivethe reference current IR. The current mirror MR21 transmits thereference current IR to the current mirror MR22 by the mirroring method.Then, the current mirror MR22 receives the reference current IR, throughthe mirroring method, the reference current IR is transmitted to thecurrent output pin OUPAD2 which the current mirror MR22 is coupled to.

Similarly, the current mirror MR22 further includes a transistor T2. Thereference current IR is transmitted to the functional block circuit 3211through a drain of the transistor T2. Wherein, through the mirroringmethod, the reference current IR is transmitted to the functional blockcircuit 3211 by the transistor T2 with a ratio of 1:1.

In the FIG. 3C, the first gate driving chip 310 and the second gatedriving chip 321 have a current mirror MR11 and a current mirror MR22respectively. Wherein, the current mirror MR11 in the first gate drivingchip 310 is composed by utilizing a N-type transistor TN1 and a N-typetransistor TN2, and the current mirror MR22 in the second gate drivingchip 321 is composed by utilizing a P-type transistor TP1 and a P-typetransistor TP2. The implementation detail between FIG. 3C and FIG. 3Bare the same, hence the detail description is omitted thereto.

It should be noted that the current mirrors MR11 and MR22 receives anadjustment signal TRIM1 and an adjustment signal TRIM2 respectively. Thecurrent mirrors MR11 and MR22 may respectively adjust the referencecurrent IR according to the adjustment signals TRIM1 and TRIM2. Theadjustment of the reference current IR described above may be attainedby adjusting at least one of the width-to-length ratios of thetransistors TN1, TN2, TP1, and TP2 through the adjustment signals TRIM1and TRIM2. The detail regarding to the width-to-length ratio of atransistor is apparent to one of the ordinary skill in the art, hencethe detail description is omitted thereto.

Referring to FIG. 4A, FIG. 4A is a diagram illustrating a gate drivingapparatus 400 according to another exemplary embodiment of the presentinvention. The gate driving apparatus 400 includes a referenceelectrical signal generator VS1, a first gate driving chip 410, and asecond gate driving chip 420. In the present embodiment, the referenceelectrical signal generator VS1 is a voltage source, which is coupledbetween an input pin INPAD1 of the first gate driving chip 310 and areference ground voltage GND. The reference electrical signal generatorVS1 generates a reference electrical signal ES1 as a voltage signal, thefirst gate driving chip 410 converts the reference electrical signal ES1to generate the reference current IR, and transmits the referencecurrent IR to a functional block circuit 411 in the first gate drivingchip 410 and the current output pin OUPAD1 of the first gate drivingchip 410 through the input pin INPAD1.

A current input pin INPAD2 of the second gate driving chip 421 iscoupled to the current output pin OUPAD1 of the first gate driving chip410, and receives the reference current IR. The reference current IR istransmitted to a functional bock circuit 4211 in the second gate drivingchip 421 and a current output pin OUPAD2 of the second driving chip 421through the current input pin INPAD2.

From the description above, the functional block circuit 411 in thefirst gate driving chip 410 and the functional block circuit 4211 in thesecond gate driving chip 421 receives identical reference current IR.Therefore, no variations are generated between an output signal GD1 andan output signal GD2 by the affect of the fabrication parameters betweenthe first gate driving chip 410 and the second gate driving chip 421,wherein the output signals GD1 and GD2 are generated by the functionalblock circuit 411 and the functional block circuit 4211 respectively. Inother words, the uniformity of the output signals GD1 and GD2 generatedby the gate driving apparatus 400 may be enhanced.

Referring to FIGS. 4B-4C, FIGS. 4B-4C respectively illustrate differentimplementations of the gate driving apparatus 400 according to theembodiment of the present invention. In FIG. 4B, the first gate drivingchip 400 further includes a voltage-current converter 412, thevoltage-current converter 412 is coupled to the input pin INPAD1 toreceive a reference electrical signal ES1. Wherein the referenceelectrical signal ES1 is to be a reference voltage, the voltage-currentconverter 412 converts the reference electrical signal ES1 to generatethe reference current IR according to the reference voltage. Thevoltage-current converter 412 includes two current mirrors MR11 andMR12. The current mirror MR11 receives the reference electrical signalES1 to be a bias voltage, and generates the reference current IRaccording to the reference electrical signal ES1. The current mirrorMR11 transmits the reference current IR to the current mirror MR12 whichis coupled to the current mirror MR11 by the mirroring method.

The current mirror MR12 is coupled between the current mirror MR11 andthe current output pin OUPAD2. The current mirror MR12 receives thereference current IR, and transmits the reference current IR to thecurrent output pin OUPAD2 through the mirroring method.

In FIG. 4C, the voltage-current converter 412 only includes a set ofcurrent mirror MR11, and the second gate driving chip 412 only includesa set of current mirror MR21. Wherein, the implementation detail of theFIG. 4C is identical as the implementation illustrated in FIG. 4B.Hence, the detail description is omitted thereto.

Referring to FIG. 5A, FIG. 5A illustrates an implementation of the firstgate driving chip of the gate driving apparatus according to theembodiment of the present invention. In the present implementation, thefirst gate driving chip 510 includes a functional block circuit 511, aselector 512, a reference electrical signal generator 513, an input pinINPAD1, and a current output pin OUPAD1. The reference electrical signalgenerator 513 is established inside of the first gate driving chip 510.The selector 512 is coupled between the reference electrical signalgenerator 513 and the input pin INPAD1. The selector 512 may selectbetween a reference electrical signal ESI generated by the referenceelectrical generator 513 and a reference electrical signal ESO inputtedexternally through the input pin INPAD1 to input. The first gate drivingchip 510 generates the reference current IR according to the result (areference electrical signal ES1) selected by the selector 512.

In other words, when the reference electrical signal ES1 is a voltagesignal, the first gate driving chip 510 may generate the referencecurrent IR according to the reference electrical signal ES1 byconverting voltage to current. When the reference electrical signal ES1is a current signal, the first gate driving chip 510 may use thereference electrical signal ES1 as the reference current IR.

Referring to FIG. 5B, FIG. 5B illustrates an implementation of theselector 512 according to the embodiment of the present invention. Theselector 512 includes a switch SW1 and a switch SW2, the switch SW1 isconnected in series between the input pin INPAD1 and an output terminalOT of the selector 512, and the switch SW2 is connected in seriesbetween the reference electrical signal generator 513 and the outputterminal OT of the selector 512. When the switch SW1 is closed, theswitch SW1 selectively transmits the reference signal ESO transmittedfrom the input pin INPAD1 to the output terminal OT of the selector 512.On the contrary, when the switch SW2 is closed, the switch SW2selectively transmits the reference electrical signal ESI transmittedfrom the reference electrical signal generator 513 to the outputterminal OT of the selector 512. Moreover, the switches SW1 and SW2 donot closed simultaneously.

Referring FIG. 6, FIG. 6 is a diagram illustrating a gate drivingapparatus 600 according to an embodiment of the present invention. Thegate driving apparatus 600 includes a first gate driving chip 610 and asecond gate driving chip 621. The first gate driving chip 610 includes afunctional block circuit 611, a switch SW3, a reference electricalsignal generator IS2, an input pin INPAD1, and a current output pinOUPAD1. The second gate driving chip 621 includes a functional blockcircuit 6211, a switch SW4, a transmission line TL1, an input pinINPAD2, and a current output pin OUPAD2. Wherein, in the first gatedriving chip 610, the reference electrical signal generator IS2 is acurrent source, which is configured to provide the reference current IR.Between the first gate driving chip 610 and the second gate driving chip621, the input pin INPAD2 is coupled to the current output pin OUPAD1,and the reference current IR is transmitted to the second gate drivingchip 621 from the first gate driving chip 610 accordingly. In the secondgate driving chip 621, the transmission line TL1 is coupled between theinput pin INPAD2 and the current output pin OUPAD2, which is configuredto transmit the reference current IR to the second gate driving chip ofnext level.

The switch SW3 is connected in series between the functional blockcircuit 611 and the reference electrical signal generator IS2, theswitch SW4 is connected in series between the functional block circuit6211 and the reference electrical signal generator IS2. When theswitches SW3 and SW4 are closed, the reference current IR is transmittedto the functional block circuit 611 and the functional block circuit6211 respectively.

Referring to FIG. 7A, FIG. 7A is diagram illustrating a gate drivingapparatus 700 according to other one embodiment of the presentinvention. The gate driving apparatus 700 includes a first gate drivingchip 710 and a programmable reference electrical signal generator 701.The programmable reference electrical signal generator 701 is coupled toan input pin INPAD1 of the first gate driving chip 710 to transmit areference electrical signal ES1. The current output pin OUPAD1 of thefirst gate driving chip 710 is coupled to a first level second gatedriving chip (not shown).

The programmable reference electrical signal generator 701 has aprogrammable interface for receiving a command signal SPIS. Theprogrammable reference electrical signal generator 701 generates thereference electrical signal ES1 according to the command signal SPIS.Wherein the programmable interface may be a serial peripheral interface.

Referring to FIG. 7B, FIG. 7B illustrates an implementation of theprogrammable reference electrical signal generator 701 according to theembodiment of the present invention. The programmable referenceelectrical signal generator 701 includes a command register 7111 and areference electrical signal generator 7012. The command register 7011receives and temporally stores the command data transmitted by thecommand signal SPIS. The reference electrical signal generator 7012 iscoupled to the command register 7011 and the input pin INPAD1. Thereference electrical signal generator 7012 generates and/or adjusts thereference electrical signal ES1 according to the command signal SPIS.

By the programmable reference electrical signal generator 701, the gatedriving apparatus 700 of the gate driving apparatus may provide users aprogrammable interface to adjust the amount of the reference current inthe gate driving apparatus 700. Hence the voltage drop rate of theoutput signal generated by the gate driving apparatus 700 may beadjusted.

Referring to FIG. 8A, FIG. 8A is a diagram illustrating a gate drivingapparatus 800 according to the embodiment of the present invention. Thegate driving apparatus 800 includes a plurality of gate driving chips810-8N0 and a current sinker 801. The gate driving chips 810-8N0 have aplurality of common pins EPAD1-EPADN, and the common pins EPAD1-EPADN ofthe gate driving chips 810-8N0 are coupled to each other. One end of thecurrent sinker 801 is coupled to the common pins EPAD1-EPADN of the gatedriving chips 810-8N0, and another end of the current sinker 801 iscoupled to the reference ground voltage GND. The current sinker 801 isconfigured to drain the reference current IR to the reference groundvoltage GND from each of the common pins EPAD1-EPADN of the gate drivingchips 810-8N0. Wherein each of the gate driving chips 810-8N0 generatesat least one output signal GD1-GDN. Each of the gate driving chips810-8N0 enables the output signals GD1-GDN to be pulled-up to thedriving voltage according to a control signal, or pulled-down to thereference ground voltage GND by the current sinker 801.

It should be noted that, in the present embodiment, the currentgenerator provides all the reference current IR that are configured topull-down the output signals GD1-GDN of the gate driving chips 810-8N0.Therefore, the capabilities of pulling-down the output signals GD1-GDNof the gate driving chips 810-8N0 are the same. In other words, thepull-down rate of the output signals GD1-GDN are the same.

Furthermore, the reference ground voltage GND may be a voltage level ofzero volts or any other nonzero voltage level.

Referring to FIGS. 8B-8E, FIGS. 8B-8E respectively illustrate differentimplementations of a gate driving apparatus 800 according to theembodiment of the present invention. In FIG. 8B, the gate drivingapparatus 800 includes a gate driving chip 810 and a gate driving chip820. The gate driving chip 810 includes a gate driving circuit composedby a controller 811, a transistor T1, and a transistor T2. The gatedriving chip 820 includes a gate driving circuit composed by acontroller 821, a transistor T3, and a transistor T4. According to aclock signal CKV, the controllers 811 and 821 provide control signals togates of the transistors T1-T2 and gates of the transistors T3-T4respectively. In the gate driving chip 810, a first terminal of thetransistor T1 is coupled to a second reference voltage (the secondreference voltage is a driving voltage VGH in the present embodiment), acontrol terminal of the transistor T1 is the gate of the transistor T1,and a second terminal of the transistor T1 generates the output signalGD1. A first terminal of the transistor T2 is coupled to the secondterminal of the transistor T1, a control terminal of the transistor T2is the gate of the transistor T2, and the second terminal of thetransistor T2 is coupled to the common pin EPAD1 of the gate drivingchip 810.

In the gate driving chip 820, a first terminal of the transistor T3 iscoupled to the driving voltage VGH, a control terminal of the transistorT3 is the gate of the transistor T3, and a second terminal of thetransistor T3 generates the output signal GD2. A first terminal of thetransistor T4 is coupled to the second terminal of the transistor T3, acontrol terminal of the transistor T4 is the gate of the transistor T4,and a second terminal of the transistor T4 is coupled to the common pinEPAD2 of the gate driving chip 820.

In the present embodiment, the current sinker 801 is a resistor R, theresistor R is connected in series between the common pins EPAD1-EPAD2and a first reference voltage (the first reference voltage is thereference ground voltage GND in the present embodiment). When thetransistor T2 is turned on, the output signal GD1 is pulled-down by thereference current IR generated by the resistor R, and drops the voltagelevel of the output signal GD1 to the reference ground voltage GND.

In FIG. 8C, the current sinker 801 is a current source IS3. The currentsource IS3 is configured to provide the reference current IR which flowsto the reference ground voltage GND from one of the common pinsEPAD1-EPAD2 to pull-down the output signals GD1 or GD2.

In FIG. 8D, the gate driving chip 810 includes a plurality of gatedriving circuits 811-813. Every gate driving circuits 811-813 arecoupled to the common pin EPAD1, and coupled to the current sinker 801by the common pin EPAD1.

In FIG. 8E, the gate driving circuits in the gate driving chips 810 and820 further include a plurality of sub-driving circuits. By using gatedriving chip 810 as example, the gate driving chip 810 includes aplurality of sub-driving circuits 8111-811N. By using the sub-drivingcircuit 8111 as example, the sub-driving circuit 8111 includes asub-controller CT1, a transistor T5, and a transistor T6. Thesub-controller CT1 generates a sub-control signal, and the sub-controlsignal is transmitted to control terminals of the transistors T5 and T6.A first terminal of the transistor T5 receives the output signal GD1,and a second terminal of the transistor T5 generates a sub-output signalSGD11. A first terminal of the transistor T6 receives the sub-outputsignal SGD11, and a second terminal of the transistor T6 is coupled to athird reference voltage (the third reference voltage is a drivingvoltage VGL in the present embodiment).

Referring to FIG. 9A-9C, FIG. 9A-9C respectively illustrate differentimplementations of a gate driving apparatus 900 according to theembodiment of the present invention. In FIG. 9A, the gate drivingapparatus 900 includes a gate driving chip 910, a gate driving chip 920,and a current generator 901. The gate driving chips 910 and 920 have twocommon pins EPAD1 and EPAD2 respectively, the common pins EPAD1 andEPAD2 are coupled with each other. One end of the current generator 901is coupled to the common pins EPAD1 and EPAD2 of the gate driving chips910 and 920. Another end of the current generator 901 is coupled to afirst reference voltage (the first reference voltage is a drivingvoltage VGH in the present embodiment). The current generator 901provides the reference current between the common pins EPAD1, EPAD2 ofthe gate driving chips 910, 920 and the driving voltage VGHrespectively.

The gate driving chip 910 includes at least one of the gate drivingcircuits 911-91N, the gate driving chips 920 includes at least one ofthe gate driving circuits 921-92N. By using the gate driving circuit 911as example, the gate driving circuit 911 includes a controller CT1 andtwo transistors T1 and T2. The transistor T1 has a first terminal, asecond terminal and a control terminal. The first terminal of thetransistor T1 is coupled to a second reference voltage (the secondreference voltage is a reference ground voltage GND in the presentembodiment), the second terminal of the transistor T1 generates anoutput signal GD1, wherein the control terminal of the transistor T1receives a control signal generated by the controller CT1. Thetransistor T2 has a first terminal, a second terminal, and a controlterminal. The first terminal of the second transistor T2 is coupled tothe second terminal of the transistor T1, the control terminal of thetransistor T2 receives the control signal generated by the controllerCT1, and the second terminal of the transistor T2 is coupled to thecorresponding common pin EPAD1. In the present implementation, thecurrent generator 901 is composed by the resistor R.

In FIG. 9B, the current generator 901 is composed by a current sourceIS3, which is different from the implementation in FIG. 9A.

Furthermore, in FIG. 9C, the gate driving circuit 911 in the gatedriving chip 910 further includes a plurality of sub-driving circuit9111-911M. By using the sub-driving circuit 9111 as example, thesub-driving circuit 9111 includes a sub-controller CT11, a transistorT5, and a transistor T6. A first terminal of the transistor T6 receivesthe output signal GD1, a second terminal of the transistor T6 generatesoutput signal SGD11, wherein a control terminal of the transistor T6receives a sub-control signal generated by the sub-controller CT11. Afirst terminal of the transistor T5 is coupled to a sub-output signalSGD11, a second terminal of the transistor T5 receives the firstreference voltage (the first reference voltage equals to the drivingvoltage VGH), wherein a control terminal of the transistor T5 receivesthe sub-control signal generated by the sub-controller CT11.

In addition, the current generator 901 of the present embodiment isconnected in series between the common pins EPAD1, EPAD2 and a drivingvoltage VGHM.

In summary, through the identical reference currents of the plurality ofgate driving chips in the gate driving apparatus, each of the gatedriving apparatus may pull-down and/or pull-up the output signalsgenerated according to the identical reference currents received.Therefore, uniformity of the output signals is maintained, andefficiency of the gate driving apparatus is enhanced.

Although the present invention has been described with reference to theabove embodiments, however, the present invention is not limitedthereto. It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of thedisclosure without departing from the scope or spirit of the disclosure.In view of the foregoing, it is intended that the disclosure covermodifications and variations of this disclosure provided they fallwithin the scope of the following claims and their equivalents.

What is claimed is:
 1. A gate driving apparatus, comprising: a firstgate driving chip, the first gate driving chip comprises a input pin anda first current output pin, the first gate driving chip receives areference electrical signal through the input pin and generates areference current according to the reference electrical signal, thefirst current output pin outputs the reference current; and N secondgate driving chips, the second gate driving chips are coupled with eachother in series, each of the second gate driving chips comprises acurrent input pin and a second current output pin, the reference currentis received through the current input pin and outputted by the secondcurrent output pin, the current input pin of the first chip of thesecond gate driving chips is coupled to the first current output pin ofthe first gate driving chip to receive the reference current, N is apositive integer, wherein, the first gate driving chip and the secondgate driving chips further respectively generate at least one firstoutput signal and at least N second output signals according to thereference current.
 2. The gate driving apparatus as claimed in claim 1,wherein the first gate driving chip comprises: a voltage-currentconverter, coupled to the input pin to receive the reference electricalsignal, wherein the reference electrical signal is a reference voltage,the voltage-current converter generates the reference current byconverting the reference voltage.
 3. The gate driving apparatus asclaimed in claim 2, wherein the voltage-current converter comprises: atleast one current mirror, to receive the reference voltage as a biasvoltage and generates the reference current according to the referencevoltage, the current mirror is coupled to the first current output pin,and the current mirror mirrors the reference current to output thereference current from the first current output pin.
 4. The gate drivingapparatus as claimed in claim 1, wherein the first gate driving chipcomprises: at least one current mirror, configured to receive thereference electrical signal of current signal, and mirrors the referenceelectrical signal to generate the reference current, the current mirroris coupled to the first current output pin, and the reference current isoutputted by the first current output pin.
 5. The gate driving apparatusas claimed in claim 1, wherein each of the second gate driving chipscomprises: at least one current mirror, configured to receive thereference electrical signal of current signal, and mirrors the referenceelectrical signal to generate the reference current, the current mirroris coupled to the first current output pin, and the reference current isoutputted by the first current output pin.
 6. The gate driving apparatusas claimed in claim 1, wherein the first gate driving chip comprises: areference electrical signal generator, coupled to the input pin andconfigured to generate the reference electrical signal.
 7. The gatedriving apparatus as claimed in claim 6, wherein the first gate drivingchip further comprises: a selector, coupled between a coupling path ofthe reference electrical signal generator and the input pin, though theselector, the first gate driving chip selectively receives the referenceelectrical signal generated from outside of the first gate driving chipor the reference electrical signal generated by the reference signalgenerator according to a selection signal.
 8. The gate driving apparatusas claimed in claim 6, wherein the reference electrical signal generatoris a current source, configured to generate the reference electricalsignal of current signal as the reference electrical current, whereinthe current source is coupled to the first current output pin through afirst transmission line, and the reference current is transmitted to thefirst current output pin through the first transmission line.
 9. Thegate driving apparatus as claimed in claim 8, wherein each of the secondgate driving chips comprises a second transmission line, the secondtransmission line is coupled between the current input pin of each ofthe second gate driving chips and the second current output pin of eachof the second gate driving chips.
 10. The gate driving apparatus asclaimed in claim 1, wherein further comprising: a programmable referenceelectrical signal generator, coupled to the input pin, the programmablereference electrical signal generator comprises a programmable interfaceto receive a command signal, the programmable reference electricalsignal generator generates the reference electrical signal according tothe command signal.
 11. The gate driving apparatus as claimed in claim10, wherein the programmable reference electrical signal generatorcomprises: a command register, configured to receive and store temporarythe command signal; and a reference electrical signal generator, coupledto the command register and the input pin, the reference electricalsignal is generated and/or adjusted according to the command signal. 12.The gate driving apparatus as claimed in claim 10, wherein theprogrammable interface is a serial peripheral interface.
 13. The gatedriving apparatus as claimed in claim 1, wherein the first gate drivingchip comprises: a first functional block circuit, configured to receivethe reference current and generates the first output signal according tothe reference current, each of the second gate driving chips comprises:a second functional block circuit, configured to receive the referencecurrent and generates the at least one second output signal according tothe reference current.
 14. A gate driving apparatus, comprising: aplurality of gate driving chips, each of the gate driving chipscomprises a common pin, the common pins of the gate driving chips arecoupled to each other; and a current generator, one end of the currentgenerator is coupled to the common pin of each of the gate drivingchips, another end of the current generator is coupled to a firstreference voltage, a reference current is provided between the commonpin of each of the gate driving chips and the first reference voltage bythe current generator, wherein, each of the gate driving chips generatesat least one output signal, each of the gate driving chips is enabled totransition the output signal between the first reference voltage and asecond reference voltage according to a control signal.
 15. The gatedriving apparatus as claimed in claim 14, wherein each of the gatedriving chips comprises at least one gate driving circuit, the gatedriving circuit comprises: a first transistor, comprising a firstterminal, a second terminal, and a control terminal, the first terminalof the first transistor is coupled to the second reference voltage, thesecond terminal of the first transistor generates the output signal,wherein the control terminal of the first transistor receives thecontrol signal; and a second transistor, comprising a first terminal, asecond terminal, and a control terminal, the first terminal of thesecond transistor is coupled to the second terminal of the firsttransistor, the control terminal of the second transistor receives thecontrol signal, and the second terminal of the second transistor iscoupled to the corresponding common pin.
 16. The gate driving apparatusas claimed in claim 15, wherein when the first reference voltage is areference ground voltage, the second reference voltage is a drivingvoltage, when the first reference voltage is a driving voltage, thesecond reference voltage is the reference ground voltage.
 17. The gatedriving apparatus as claimed in claim 15, wherein the gate drivingcircuit further comprises: a plurality of sub-driving circuits,configured to receive the output signal, each of the sub-drivingcircuits comprising: a sub-controller, configured to generate asub-control signal; a third transistor, having a first terminal, asecond terminal, and a control terminal, the first terminal of the thirdtransistor receives the output signal, the second terminal of the thirdtransistor generates a sub-output signal, wherein the control terminalof the third transistor receives the sub-control signal; and a fourthtransistor, comprising a first terminal, the second terminal, and acontrol terminal, the first terminal of the fourth transistor is coupledto the sub-output signal, the second terminal of the fourth transistoris coupled to a third reference voltage, wherein the control terminal ofthe fourth transistor receives the sub-control signal.
 18. The gatedriving apparatus as claimed in claim 14, wherein the current generatoris a resistor, the resistor is connected in series between the commonpin of each of the gate driving chips and the first reference voltage.19. The gate driving apparatus as claimed in claim 14, wherein theresistor is a variable resistor.
 20. The gate driving apparatus asclaimed in claim 14, wherein the current generator is a current source,configured to generate the reference current.